IBM Kingston
Live Status: Currently, the IBM Kingston is Online via IBM Quantum Platform (0 jobs). Updated real-time for IBM Quantum circuit monitoring.
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Live Network Load
IBM Quantum Platform
*Metric: Total number of jobs pending execution (Queue Depth) on ibm_kingston via IBM Quantum Platform.
Reserved Access
On-Premises
System Availability Trends
Detailed Connectivity (Last 7 Days)
Unofficial Telemetry Dashboard
This is an independent tracking project. QPUStatus is not affiliated with, endorsed by, or partnered with IBM or IBM Quantum. Our data is gathered automatically via public API routing endpoints and may not perfectly reflect internal hardware states. For authoritative information, visit the IBM Quantum Platform.
Hardware Deep Dive
IBM Kingston (ibm_kingston) is a Heron r2 processor system, sharing the same 156-qubit architecture as ibm_fez and ibm_marrakesh, including tunable couplers and TLS mitigation. IBM names its cloud QPUs after cities. Like other Heron r2 systems, ibm_kingston runs on IBM Quantum System Two inside a dilution refrigerator cooled to approximately a hundredth of a degree above absolute zero. As of March 2026, live calibration data from the IBM Quantum Platform shows ibm_kingston achieving a median two-qubit gate error of 2.02×10-3, a median T1 of 267.71 µs, and 340,000 CLOPS, placing it among the higher-throughput systems in the current public Heron fleet alongside ibm_boston.
Technical Specifications
Common Provider Questions
What is the difference between the "median 2Q gate error" and the "layered 2Q gate error" shown on the IBM Quantum Platform?
The median 2Q gate error (sometimes called EPLG per edge) is the error rate measured on a single isolated two-qubit gate in a standard randomised benchmarking experiment. It reflects the best-case fidelity for a single gate in isolation. The layered 2Q gate error is a newer metric IBM introduced to better reflect real circuit performance: it measures error per gate when many two-qubit gates are executed simultaneously across the chip in a single layer, which is how circuits actually run. Simultaneous execution introduces additional crosstalk between gates that the single-gate measurement does not capture. For ibm_kingston, the layered figure (3.32×10-3) is approximately 64% higher than the isolated figure (2.02×10-3), which is typical for Heron r2 systems. When estimating whether your circuit will succeed, the layered metric is generally the more realistic number to use. IBM's QPU information guide documents both metrics in detail.
Official Resources
IBM Quantum Platform — Compute Resources
Live queue depth, calibration data, and current error rates for ibm_kingston directly from IBM Quantum Platform. Sign-in required.
IBM Quantum Processor Types Documentation
Official documentation covering the Heron r2 architecture, TLS mitigation, revision changelog versus r1, and native gate set.
IBM QDC 2024 Blog
Official IBM Quantum Developer Conference 2024 writeup covering the Heron r2 processor family, the 5,000 two-qubit gate milestone, and TLS mitigation.
QPU Information Guide
Explanation of all metrics displayed on the IBM Quantum Platform, including CLOPS_h, EPLG, layered 2Q error, T1, T2, and readout error definitions.